1. Field of the Invention
The present invention generally relates to semiconductor integrated device design and fabrication and, more particularly, to techniques for improving hot carrier resistance in ULSI transistors, such as CMOSFETs in random access memories (RAMs).
2. Description of the Related Art
In the past ten years, the scale of integration of semiconductor devices has increased significantly. More and more devices, such as CMOS type devices, have been positioned on smaller and smaller sized silicon substrates. In this trend toward higher packing density, the channel lengths of insulated gate field effect transistors have been drastically decreased to fabricate the smaller devices needed for these higher scale integration integrated circuits. However, as the devices approach the sub-micron level for CMOS technology, the channel length of the CMOS devices are so small that functional problems result.
In particular, source/drain punchthrough and hot electron susceptibility are the most critical detrimental short channel effects in CMOS device structures. Source/drain punchthrough occurs when the depletion regions of both the source and the drain of a transistor meet in the channel therebetween and create a depleted region extending from the drain region to the source region. Hence, the inverted channel region, which is located under the gate oxide, is lost due to overlapping source and drain regions. This situation eliminates gate control over the transistor and causes significant current leakages, especially when the transistor is in the "off" state. Presently, this effect can be reduced by positioning antipunchthrough implants in the channel regions during the fabrication process, such as Boron for n-channel devices and Phosphorus or Arsenic for p-channel devices, that prevent the depletion regions from meeting.
The other important problem that results from the short channel structures resulting from sub-micron CMOS dimension is hot electron susceptibility which is defined as the injection of high energy electrons into the gate oxide layer and farther into the polysilicon forming the gate of the CMOS structure. This electron injection into the gate oxide is mainly caused by the high electric field occurring at the drain contact of the transistor and severely reduces the threshold voltage of the transistor. In general, hot electron injection can be reduced by oxidizing the gate edge next to the drain region. Thus, oxidation rounds the gate edge and increases the gate oxide thickness at the gate edges. However, in ULSI applications, the oxide is not a good dielectric for the higher electric fields in these applications.
Alternatively, lightly-doped drain (LDD) structures, which are uniquely designed drain structures, are also advantageously used to overcome the hot electron injection problem. Particularly, in an LDD structure, the source/drain regions are formed by implanting two different ions with different doping densities. As a result, a lightly doped drain region, which is adjacent the channel region, separates the channel region from a heavily doped drain region. This lightly doped region significantly reduces the high electric field which causes hot electron injection into the gate oxide. However, ever decreasing device dimensions have brought many constraints to conventional LDD process technologies.
Specifically, in CMOS ULSI applications, a proper LDD drain should provide adequate hot-carrier protection for the device. In fact, there are many approaches in CMOS technology to provide such optimum LDD structures to prevent hot-electron injection into the gate oxide. One important technique is nitrogen implantation into the source/drain regions during the manufacture of NMOSFETs and PMOSFETs prior to the sidewall-spacer (SiO.sub.2) formation. After the sidewall SiO.sub.2 spacer deposition, the implanted nitrogen atoms are segregated at the interface between the substrate and the sidewall SiO.sub.2 by a low temperature heat treatment. This forms a silicon nitride layer under the sidewall SiO.sub.2 which can suppress the hot electron injection.
However, this technique limits the nitrogen atom segregation to the area under the SiO.sub.2 sidewall. Due to the high electric field strength, the structure cannot suppress the hot carrier injection into the gate oxide, since the nitrogen segregated area only covers the region under the CVD deposited SiO.sub.2 sidewall spacer.
Hence, there is a need for processing techniques that are more suited for preventing punchthrough and hot carrier degradation of CMOS FETs in ULSI applications. There is a particular need for processing techniques that are capable of preventing hot carrier injection into the gate of the transistor.